1. Field of the Invention
The present invention relates to a data processing apparatus employing the direct memory access (DMA) procedure, and more particularly to a data processing apparatus wherein a host processor, a memory and a peripheral controller transfer data from one to another through a common data bus.
2. Description of the Prior Art
A DMA system is the system in which data can be directly transmitted between the peripheral controller and the memory without intervention of the host processor. Such data transmission is called the DMA transmission and is widely used in a conventional data processing apparatus wherein the host processor, the memory and the peripheral controller are coupled to each other by a common data bus. The DMA transmission must be performed in a period when the common bus is in an idle state, that is, when the host processor does not use the common bus.
In general, to give the right of bus usage to the peripheral controller, a DMA controller is employed in the above described data processing apparatus. The DMA controller is inserted between the host processor and the peripheral controller, and sends a DMA request signal to the host processor according to an access request from the peripheral controller. In response to the reception of the request signal, the host processor checks whether it is itself utilizing the bus utilizing at this time. This checking operation is in general executed by software, for instance a DMA interruption program. As the result, if the host processor does not need to use the bus, the bus usage right is granted at this time to the peripheral controller. On the other hand, if the host processor is using the bus or needs to use the bus at this time, the bus usage right is not granted to the peripheral controller until its host processor has finished the use of the bus. The DMA controller grants the bus usage right to the peripheral controller according to the result of the aforementioned checking operation by the host processor.
However, the check operation requires a long period of time since the DMA interruption program is executed by software. Particularly, the host processor starts the checking operation after receiving the DMA request signal from the DMA controller, and therefore a quick response for the DMA request can not be obtained in the conventional data processing apparatus.
Further, in the case that a display controller, a disk controller, etc. are employed as a peripheral controller, a high-speed DMA transmission is particularly required because a large number of data bits must be manipulated. Since such peripheral controllers need a large number of DMA transmissions, a quick response between the host processor and the DMA controller is necessary. However, as described above, the conventional data processing apparatus spends a significant time in the checking operation, and therefore it is unsuitable for the high-speed DMA transmission.